Nilesh R. Shah

C-309

Academic block C

I am a PhD candidate in the Department of Computer Science and Engineering at IIT Hyderabad, under the supervision of Dr. Ramakrishna Upadrasta. As a member of the Scalable Compilers for Heterogeneous Architectures group, I focus on advancing compiler technologies for diverse computing environments. I hold an M.Tech in Computer Science and Engineering from IIT Hyderabad (2022) and a B.Tech in Computer Science and Engineering from UIT-RGPV (2018).

My research interests lie in compiler optimizations, particularly utilizing Polyhedral compilation techniques, MLIR and performance tools for HPC. My work involves static analysis and memory-based optimizations, with a specific focus on designing scalable analytical cache models. These models serve as cost metrics for loop-based optimizations such as loop tiling and fusion, which are crucial for enhancing the time and energy efficiency of deep learning applications.

Recent Activities

Jul 10, 2023	Selected for 19th International Summer School on ACACES, 2023 organized by HiPEAC Network in Fiuggi, Italy.
Jan 17, 2023	Accepted presentation and talk on “GeMS: Towards Generating Millions of SCoPs” in IMPACT 2023 workshop (associated with HIPEAC 2023).
Nov 17, 2022	Paper title “BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation” accepted in ACM TACO.
Aug 27, 2022	Awarded Kesav Nori research excellence award for Best MTech thesis in Systems.
Jun 01, 2022	Completed MTech in Computer Science and Engineering from IIT Hyderabad!

Publications

TACO

BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation

Nilesh Rajendra Shah , Ashitabh Misra , Antoine Miné , and 2 more authors

ACM Trans. Archit. Code Optim., Nov 2022

Abs

For Affine Control Programs or Static Control Programs (SCoP), symbolic counting of reuse distances could induce polynomials for each reuse pair. These polynomials along with cache capacity constraints lead to non-affine (semi-algebraic) sets; and counting these sets is considered to be a hard problem. The state-of-the-art methods use various exact enumeration techniques relying on existing cardinality algorithms that can efficiently count affine sets.We propose BullsEye , a novel, scalable, accurate, and problem-size independent approximation framework. It is an analytical cache model for fully associative caches with LRU replacement policy focusing on sampling and linearization of non-affine stack distance polynomials. First, we propose a simple domain sampling method that can improve the scalability of exact enumeration. Second, we propose linearization techniques relying on Handelman’s theorem and Bernstein’s representation. To improve the scalability of the Handelman’s theorem linearization technique, we propose template (Interval or Octagon) sub-polyhedral approximations.Our methods obtain significant compile-time improvements with high-accuracy when compared to HayStack on important polyhedral compilation kernels such as nussinov, cholesky, and adi from PolyBench, and harris, gaussianblur from LLVM-TestSuite. Overall, on PolyBench kernels, our methods show up to 3.31\texttimes (geomean) speedup with errors below ≈ 0.08% (geomean) for the octagon sub-polyhedral approximation.