Nilesh R. Shah
PMRF Research Fellow at CSE department, IIT Hyderabad
![nilesh_pic.jpg](/assets/img/nilesh_pic.jpg?f374ec41a582cc606b18c35b93ccabe8)
C-309
Academic block C
I am a PhD candidate in the Department of Computer Science and Engineering at IIT Hyderabad, under the supervision of Dr. Ramakrishna Upadrasta. As a member of the Scalable Compilers for Heterogeneous Architectures group, I focus on advancing compiler technologies for diverse computing environments. I hold an M.Tech in Computer Science and Engineering from IIT Hyderabad (2022) and a B.Tech in Computer Science and Engineering from UIT-RGPV (2018).
My research interests lie in compiler optimizations, particularly utilizing Polyhedral compilation techniques, MLIR and performance tools for HPC. My work involves static analysis and memory-based optimizations, with a specific focus on designing scalable analytical cache models. These models serve as cost metrics for loop-based optimizations such as loop tiling and fusion, which are crucial for enhancing the time and energy efficiency of deep learning applications.
Recent Activities
Jul 10, 2023 | Selected for 19th International Summer School on ACACES, 2023 organized by HiPEAC Network in Fiuggi, Italy. |
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Jan 17, 2023 | Accepted presentation and talk on “GeMS: Towards Generating Millions of SCoPs” in IMPACT 2023 workshop (associated with HIPEAC 2023). |
Nov 17, 2022 | Paper title “BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation” accepted in ACM TACO. |
Aug 27, 2022 | Awarded Kesav Nori research excellence award for Best MTech thesis in Systems. |
Jun 01, 2022 | Completed MTech in Computer Science and Engineering from IIT Hyderabad! |
Publications
- TACOBullsEye : Scalable and Accurate Approximation Framework for Cache Miss CalculationACM Trans. Archit. Code Optim., Nov 2022